The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device using a serial-to-parallel scheme. In particular, the invention relates to a semiconductor memory device having global input/output lines with relatively short lengths.
Typical DRAMs such as DDR/DDR2 synchronous DRAM (SDRAMs) input/output data using a serial-to-parallel scheme.
The serial-to-parallel scheme is to input/output data to/from memory cells inside the semiconductor memory device in a serial fashion, but input/output data to/from the outside of the semiconductor memory device in a parallel fashion. The number of data input/output at a time in a parallel fashion is referred to as a data bandwidth. The mode of the semiconductor memory device may be determined according to the data bandwidth.
For example, a semiconductor memory device operating in an X4 mode can input/output four bits of data at a time, and a semiconductor memory device operating in an X8 mode can input/output eight bits of data at a time. Also, a semiconductor memory device operating in an X16 mode can input/output sixteen bits of data at a time.
Meanwhile, as the SDRAM specification changes from DDR SDRAM to DDR2 SDRAM, an N-bit prefetch scheme is used to read or write data corresponding to a minimum burst length in response to one read or write command in each data (DQ) input/output buffer in order to cope with a high frequency operation, where N is equal to the minimum burst length.
A DDR SDRAM uses a 2-bit prefetch scheme to access 2-bit data stored in memory cells in each clock cycle and output the accessed 2-bit data to data pads.
Also, a DDR2 SDRAM uses a 4-bit prefetch scheme to access 4-bit data stored in memory cells in each clock cycle and output the accessed 4-bit data to data pads.
Likewise, a DDR3 SDRAM uses an 8-bit prefetch scheme to access 8-bit data stored in memory cells in each clock cycle and output the access 8-bit data to data pads.
In the semiconductor memory device, the number of global input/output lines used to input/output data may be defined according to the data bandwidth and the bit number of the prefetch.
For example, since a DDR3 SDRAM having the X8 data bandwidth uses the 8-bit prefetch scheme, 64 (=8×8) global input/output lines are needed to input/output data in one clock cycle. That is, 64 bits of data are simultaneously input/output in the semiconductor memory device.
Also, since a DDR4 SDRAM having the X16 data bandwidth uses the 16-bit prefetch scheme, 256 (=16×16) global input/output lines are needed to input/output data in one clock cycle. That is, 256 bits of data are simultaneously input/output in the semiconductor memory device.
However, if a large number of global input/output lines are simultaneously used, as described above, it is difficult to apply to the semiconductor memory device. That is, as the semiconductor memory device is becoming smaller and smaller, there occurs a problem that the global input/output lines occupy a very large area.
The conventional semiconductor memory device having a plurality of banks reduces the number of the global input/output lines by dividing each bank into a plurality of memory blocks, grouping the memory blocks into a predetermined number of memory block groups, and making the respective memory block groups share the corresponding column select signals.
FIG. 1 is a block diagram illustrating the connection configuration of global input/output lines in a conventional semiconductor memory device having a plurality of banks.
Referring to FIG. 1, the conventional semiconductor memory device includes four banks BANK0, BANK1, BANK2 and BANK3. Eight bits of data are output at a time when one memory is selected among a plurality of memory blocks U0, U1, U2, U3, U4, U5, U6, U7, D0, D1, D2, D3, D4, D5, D6 and D7 included in each of the banks BANK0, BANK1, BANK2 and BANK3. That is, eight global input/output lines are connected to each memory block. It can be seen that the conventional semiconductor memory device illustrated in FIG. 1 is a DDR3 SDRAM with an 8X data bandwidth (8-bit prefetch).
More specifically, each of the banks BANK0, BANK1, BANK2 and BANK3 is divided into upper banks U0, U1, U2, U3, U4, U5, U6 and U7 and lower banks D0, D1, D2, D3, D4, D5, D6 and D7.
Among the upper banks U0, U1, U2, U3, U4, U5, U6 and U7, the zeroth memory block U0 and the fourth memory bank U4 share the global input/output line GIO_04; the first memory block U1 and the fifth memory bank U5 share the global input/output line GIO_15; the second memory block U2 and the sixth memory bank U6 share the global input/output line GIO_26; and the third memory block U3 and the seventh memory bank U7 share the global input/output line GIO_37.
Likewise, among the lower banks D0, D1, D2, D3, D4, D5, D6 and D7, the zeroth memory block D0 and the fourth memory bank D4 share the global input/output line GIO_04; the first memory block D1 and the fifth memory bank D5 share the global input/output line GIO_15; the second memory block D2 and the sixth memory bank D6 share the global input/output line GIO_26; and the third memory block D3 and the seventh memory bank D7 share the global input/output line GIO_37.
In summary, the global input/output line GIO_04 consisting of eight lines is connected to the zeroth and fourth memory blocks U0 and U4 of each upper bank and the zeroth and fourth memory blocks D0 and D4 of each lower bank in the banks BANK0, BANK1, BANK2 and BANK3, and data are input/output therethrough.
The global input/output line GIO_15 consisting of eight lines is connected to the first and fifth memory blocks U1 and U5 of each upper bank and the first and fifth memory blocks D1 and D5 of each lower bank in the banks BANK0, BANK1, BANK2 and BANK3, and data are input/output therethrough.
The global input/output line GIO_26 consisting of eight lines is connected to the second and sixth memory blocks U2 and U6 of each upper bank and the second and sixth memory blocks D2 and D6 of each lower bank in the banks BANK0, BANK1, BANK2 and BANK3, and data are input/output therethrough.
The global input/output line GIO_37 consisting of eight lines is connected to the third and seventh memory blocks U3 and U7 of each upper bank and the third and seventh memory blocks D3 and D7 of each lower bank in the banks BANK0, BANK1, BANK2 and BANK3, and data are input/output therethrough.
FIG. 2 is a timing diagram illustrating the operation of the conventional semiconductor memory device of FIG. 1 having the plurality of banks.
Referring to FIG. 2, in which the clock signal is CLK, the conventional semiconductor memory device having the plurality of banks outputs the data in the following sequence.
First, a column enable signal YAE is toggled twice at a preset interval in response to a read command READ, as indicated by reference numeral 
The logic level of a column address signal CA<2> is changed in response to the toggling of the column enable signal YAE, as indicated by reference numeral  That is, the column address is applied to select which one of the plurality of banks BANK0, BANK1, BANK2 and BANK3 the data is output from.
At this point, the plurality of banks BANK0, BANK1, BANK2 and BANK3 are divided into the upper banks U0, U1, U2, U3, U4, U5, U6 and U7 and the lower banks D0, D1, D2, D3, D4, D5, D6 and D7. Also, since the semiconductor memory device uses the 8-bit prefetch, the data output in response to the column address is data output from one of the upper banks U0, U1, U2, U3, U4, U5, U6 and U7 or the lower banks D0, D1, D2, D3, D4, D5, D6 and D7 in the selected one of the banks BANK0, BANK1, BANK2 and BANK3. It is assumed herein that the upper banks U0, U1, U2, U3, U4, U5, U6 and U7 are selected.
As the logic level of the column address signal CA<2> changes, a first column select signal CY<i> and a second column select signal CY<j> are alternately toggled, as indicated by reference numeral  Data DATA_0, DATA_1, DATA_2 and DATA_3 stored in the zeroth to third memory blocks U0, U1, U2 and U3 of the upper banks are output through the global input/output lines in response to the toggling of the first column select signal CY<i>, and data DATA_4, DATA_5, DATA_6 and DATA_7 stored in the fourth to seventh memory blocks U4, U5, U6 and U7 of the upper banks are output through the global input/output lines in response to the toggling of the second column select signal CY<j>. That is, the zeroth to third memory blocks U0, U1, U2 and U3 of the upper blocks and the fourth to seventh memory blocks U4, U5, U6 and U7 of the upper blocks share the global input/output lines to output the data stored therein in a time division manner.
The data DATA_0, DATA_1, DATA_2 and DATA_3, DATA_4, DATA_5, DATA_6 and DATA_7 output from the upper banks through the global input/output lines are stored in prefetch latches until a data strobe signal DQS is toggled, and then are output in sequence through the predefined data (DQ) pads.
In the configuration of the memory blocks U0, U1, U2, U3, U4, U5, U6, U7, D0, D1, D2, D3, D4, D5, D6 and D7 included in each of the banks BANK0, BANK1, BANK2 and BANK3, the memory blocks sharing the column select signal are spaced relatively apart. For example, the zeroth and fourth memory blocks U0 and U4 of the upper banks are spaced farther apart than the first to third memory blocks.
That is, the global input/output lines connecting the memory blocks sharing the column select signal are relatively long.
Thus, the global input/output lines connecting the different banks are also relatively long. For example, the distance between the zeroth memory block U0 of the zeroth bank BANK0 and the fourth memory block U4 of the first bank BANK1 is relatively longer than the distance between the zeroth bank BANK0 and the first bank BANK1.
As the memory blocks sharing the column select signal are spaced farther apart, the global input/output lines must be longer. This will increase an area occupied by the global input/output lines in the semiconductor memory device. Also, the loading of data passing through the global input/output lines will increase.
As a result, data coupling seriously occurs between the adjacent global input/output lines, making it difficult to transfer data at a high speed. In addition, although it is expected that future semiconductor memory devices will be further miniaturized, it is difficult to develop miniaturized semiconductor memory devices if the global input/output lines occupy a large area therein.
Furthermore, although it is expected that future semiconductor memory devices will operate at a higher speed, it is difficult to develop high-speed semiconductor memory devices if the loading of data passing through the global input/output lines increases.